详细地讲解了absoft pro fortran 编译器的用法
2022-05-05 11:34:42 2.31MB absoft fortran compiler
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详细的介绍了VCS的仿真过程,对于想学习verilog综合软件的人来说,这是一个不过说明文档。
2022-05-05 10:28:44 376KB verilog 综合 软件
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CFortranTranslator:从Fortran到C ++的翻译器
2022-05-04 22:44:31 760KB converter parser compiler cpp
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Android Cross Compiler
2022-05-02 09:06:11 195KB android
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My career at Synopsys spanned 9 years and was focused entirely on front-end design. With each new position within the company (FAE, Trainer, Consultant, Manager) I learned more about high level design, coding styles, synthesis, scripting, optimization techniques, timing closure, timing convergence and QoR. What I have noticed about the industry today, is that it is focused on the wrong end of the development cycle. Fixing timing problems with better placement technology is more of a last ditch effort than a state of the art approach. Ultimately, if the problem can’t be fixed with placement – the designer has to go back to their RTL code and re-write it to fix the problem. Code it correctly from the beginning, anticipating implementation roadblocks and barriers, and you won’t need the big fancy tools to solve your timing convergence/closure problems later in the design cycle.
2022-04-30 15:15:02 161KB RTL Coding Design Compiler
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IC_Compiler_alone
2022-04-28 18:34:14 11KB Java
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编译器 使用 lex 和 yacc ,生成解析树和符号表
2022-04-24 20:50:00 79KB C
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compiler 编译原理课程设计,包括词法分析器(nfa转dfa)和语法分析器(LR1实现)
2022-04-23 15:03:34 8KB C++
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lexical_syntax_analysis:编译原理词法分析器和语法分析器LR(1)实现C ++
2022-04-21 16:54:40 503KB syntax compiler analysis lr1
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Design Compiler的中文教程。
2022-04-20 12:13:32 837KB Design Compiler
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