最新DFI 4.0文档,最新更新,请有需要的下载。 最新DFI 4.0文档,最新更新,请有需要的下载。
2021-05-28 20:59:44 459KB ddr
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将xilinx的ddr ctrl 的 native接口封装成多个fifo读写通道
2021-05-26 10:00:38 9KB ddr
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02_Artix FPGA DDR控制器MIG使用(AXI4)(MA703FA-35T)20190401.pdf 02_Artix FPGA DDR控制器MIG使用(AXI4)(MA703FA-35T)20190401.pdf
2021-05-23 23:29:21 4.77MB FPGA Artix DDR MIG
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Nexys4 DDR板子模块介绍和约束文件 Nexys4 DDR板子模块介绍和约束文件
2021-05-22 21:56:41 3.26MB FPGA
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Application Note: [1] Because lack of Address pin A15 in package, following SoCs do not support the 512M*8 DDR3: RK2906-6,RK2906-8,RK3066. [2]The DRAM Part Number usually consists of two parts divided by '-', which the first part contains memory type, density, orgainization, package, and the second part usually means data rate. We don't care about the second part. [3]RockChip platform can support all the chips that match the first part of Part Number which marks '√' or 'T/A', and do not nee d to care the second part. If you want your system running more effective , you may need to find out the exact data rate in DRAM datasheet and config in kernel menuconfig. [4]Please copy the Rockchip reference design model of DRAM area PCB Layout directly without any modification and follow the PCB layout rules from Rockchip. Contact information: fae@rock-chips.com [5]Only support for RK3128. [6]The DRAM's VDD and VDDQ should powered by 1.5V when it used on these SoCs.
2021-05-22 08:37:16 513KB RK
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This is quick guide shows how to use the simple version of PCIe control software
2021-05-21 10:14:29 219KB FPGA
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ddr sdram的连接原理图和pcb图,有实物图片,希望能有所帮助! pcb , 图片 Send_over.jpg (191.67 KB, 下载次数: 221) 实物图 实物图 Twister_DDR_SDRAM_Board_Manual.pdf 1.42 MB, 下载次数: 1011 , 下载积分: 资产 -2 信元, 下载支出 2 信元 原理图pcb
2021-05-13 11:31:52 1.42MB ddr sdram 原理图 pcb
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DDR3最新的规范 JESD79-3E 不是JESD79-3D
2021-05-11 19:02:59 4.92MB DDR DDR3 规范
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关于xilinx的mig ip核的使用记录
2021-05-11 09:01:32 295KB ddr
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DDR的模块分析
2021-05-02 09:00:36 1.86MB 高度电路设计
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