基于FGGA设计的音频录音与播放实验例程Verilog逻辑源码Quartus工程文件+文档说明,音频编解码芯片选用WOLFSON 公司的 WM8731 芯，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 `timescale 1ps/1ps module top ( input clk, //clock input input rst_n, //reset input input key, //record play button input wm8731_bclk, //audio bit clock input wm8731_daclrc, //DAC sample rate left right clock output wm8731_dacdat, //DAC audio data output input wm8731_adclrc, //ADC sample rate left right clock input wm8731_adcdat, //ADC audio data input inout wm8731_scl, //I2C clock inout wm8731_sda, //I2C data output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data ); parameter MEM_DATA_BITS = 16 ; //external memory user interface data width parameter ADDR_BITS = 24 ; //external memory user interface address width parameter BUSRT_BITS = 10 ; //external memory user interface burst width wire wr_burst_data_req; wire

基于FPGA设计的SD卡音乐播放Verilog逻辑源码Quartus工程文件+文档说明，音频编解码芯片选用WOLFSON 公司的 WM8731 芯，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, input key1, input wm8731_bclk, //audio bit clock input wm8731_daclrc, //DAC sample rate left right clock output wm8731_dacdat, //DAC audio data output input wm8731_adclrc, //ADC sample rate left right clock input wm8731_adcdat, //ADC audio data input inout wm8731_scl, //I2C clock inout wm8731_sda, //I2C data output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output [5:0] seg_sel, output [7:0] seg_data ); wire[9:0] lut_index; wire[31:0] lut_data; wire[3:0] state_code; wire[6:0] seg_data_0; //I2C master controller i2c_config i2c_config_m0( .rst (~rst_n ), .clk (clk ), .clk_div_cnt (16'd99 ), .i2c_addr_2byte (1'b0 ), .lut_index (lut_index ), .lut_dev_addr (lut_data[31:24] ), .lut_reg_addr (lut_data[23:8] ), .lut_reg_data (lut_data[7:0] ), .error ( ), .done ( ), .i2c_scl

基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从 ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire osd_hs; wire osd_vs; wire osd_de; wire[7:0] osd_r; wire[7:0] osd_g; wire[7:0] osd_b; assign vga_out_hs = osd_hs; assign vga_out_vs = osd_vs; assign vga_out_r = osd_r[7:3]; //discard low bit data assign vga_out_g = osd_g[7:2]; //discard low bit data assign vga_out_b = osd_b[7:3]; //discard low bit data //generate video pixel clock video_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ) ); color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b

基于FPGA设计的 AD9708 +AD9280 ADDA转换测试Verilog逻辑源码Quartus工程文件+文档说明，DA芯片选用AD公司推出的AD9708，AD芯片选用AD9280，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, //adc input[7:0] ad9280_data, output ad9280_clk, //dac output[7:0] ad9708_data, output ad9708_clk, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire grid_hs; wire grid_vs; wire grid_de; wire[7:0] grid_r; wire[7:0] grid_g; wire[7:0] grid_b; wire wave0_hs; wire wave0_vs; wire wave0_de; wire[7:0] wave0_r; wire[7:0] wave0_g; wire[7:0] wave0_b; wire adc_clk; wire adc0_buf_wr; wire[10:0] adc0_buf_addr; wire[7:0] adc0_buf_data; wire dac_clk; wire[7:0] dac_data; reg[8:0] rom_addr; assign vga_out_hs = wave0_hs; assign vga_out_vs = wave0_vs; assign vga_out_r = wave0_r[7:3]; //discard low bit data assign vga_out_g

基于FPGA设计的不同频率PWM蜂鸣器控制实验Verilog逻辑源码Quartus工程文件+文档说明，用 PWM 控制蜂鸣器，用丌同频率的 pwm 让蜂鸣器发出丌一样的响声，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module buzzer_pwm_test( input clk, input rst_n, input key1, output buzzer ); parameter IDLE = 0; parameter BUZZER = 1; wire button_negedge; wire pwm_out; reg[31:0] period; reg[31:0] duty; reg[3:0] state; reg[31:0] timer; assign buzzer = ~(pwm_out & (state == BUZZER));//buzzer low active always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin period <= 32'd0; timer <= 32'd0; duty <= 32'd429496729; state <= IDLE; end else case(state) IDLE: begin if(button_negedge) begin period <= 32'd8590; //The pwm step value state <= BUZZER; duty = 32'd12_499_999) //buzzer effictive time 250ms begin state <= IDLE; timer <= 32'd0; end else begin timer <= timer + 32'd1; end end default: begin state <= IDLE; end endcase end ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key1), .button_posedge (), .button_negedge (button_negedge), .button_out () ); ax_pwm# ( .N(32) ) ax_pwm_m0( .clk (clk), .rst (~rst_n), .period (period), .duty (duty), .pwm_out (pwm_out) ); endmodule

计算器是设计中经常用到的一个操作软件，设计和学习计算器使我们亲密的联系所学的各模块， 对我们的学习有很大的帮助和提升。希望大家来学习

FPGA设计串口收发实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module uart_test( input clk, input rst_n, input uart_rx, output uart_tx ); parameter CLK_FRE = 50;//Mhz localparam IDLE = 0; localparam SEND = 1; //send HELLO ALINX\r\n localparam WAIT = 2; //wait 1 second and send uart received data reg[7:0] tx_data; reg[7:0] tx_str; reg tx_data_valid; wire tx_data_ready; reg[7:0] tx_cnt; wire[7:0] rx_data; wire rx_data_valid; wire rx_data_ready; reg[31:0] wait_cnt; reg[3:0] state; assign rx_data_ready = 1'b1;//always can receive data, //if HELLO ALINX\r\n is being sent, the received data is discarded always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin wait_cnt <= 32'd0; tx_data <= 8'd0; state <= IDLE; tx_cnt <= 8'd0; tx_data_valid <= 1'b0; end else case(state) IDLE: state <= SEND; SEND: begin wait_cnt <= 32'd0; tx_data <= tx_str; if(tx_data_valid == 1'b1 && tx_data_ready == 1'b1 && tx_cnt < 8'd12)//Send 12 bytes data begin tx_cnt <= tx_cnt + 8'd1; //Send data counter end else if(tx_data_valid && tx_data_ready)//last byte sent is complete begin tx_cnt <= 8'd0; tx_data_valid <= 1'b0; state <= WAIT; end else if(~tx_data_valid) begin tx_data_valid <= 1'b1; end end WAIT: begin wait_cnt <= wait_cnt + 32'd1; if(rx_data_valid == 1'b1) begin tx_data_valid <= 1'b1; tx_data <= rx_data; // send uart received data end else if(tx_data_valid && tx_data_ready) begin tx_data_valid <= 1

本论文基于搭建一种具有优秀可移植性的高性能通用软件无线电平台的目的。以亚诺德半导体有限公司的射频捷变收发器AD9364为核心器件代替由分立器件搭建射频收发端，并采用了在Vivado环境用HDL语言对FPGA进行开发的方法，完成了对AD9364的控制和数据收发操作。FPGA与AD9364间的控制通路分别采用了利用UART接口，以及利用ROM IP核的进行AD9364寄存器配置的两种方法，数据接口采用了LVDS兼容模式。利用此平台实现了16APSK调制。平台通过资源占用分析和系统收发试验。得出了通用软件无线电平台的能完成数据收发且具有优秀可移植性的结论。

FPGA设计工具小软件FPGA字模提取 Image2Lcd winhex 波形数据生成器 串口调试工具 软件列表： FPGA字模提取 Image2Lcd USB转串口驱动 winhex 串口调试工具 波形数据生成器.exe

ALTERA FPGA设计Verilog设计学习资料文档资料Verilog学习教程： Cyclone IV器件手册.pdf Cyclone_IV_器件中的时钟网络与PLL.pdf Embedded Peripherals IP User Guide.pdf FPGA设计全流程.pdf Modelsim仿真技巧REV6.0.pdf TimeQuest静态时序分析REV7.0.pdf Quartus II中上拉电阻的设置方法.pdf quartus2中文手册.pdf ug_vip.pdf VerilogHDL扫盲文.pdf VerilogHDL那些事儿-整合篇.pdf VerilogHDL那些事儿_建模篇.pdf Verilog_HDL_那些事儿_时序篇.pdf verilog分享--verilog快速掌握之模块例化.pdf Verilog数字系统设计教程-夏宇闻.pdf Verilog经典教程第三版.pdf 数字逻辑设计.pdf FPGA 开发指南.pdf Nios II开发指南.pdf