Python有限状态机——transitions https://xercis.blog.csdn.net/article/details/124127799

状态机演示程序。开始时，开始按钮点亮，点击下一步，表示状态的布尔灯顺序点亮，点击下一步，按照状态三、二、一变化。

有限状态机设计技术，技术资料，简洁的介绍，加深对状态机编程的理解

DDR3控制器的SystemVerilog实现 这是一个小组项目。 该控制器通过符合Micro数据手册规格的状态机结构通过Verilog实现，并连接到预定义的DDR3存储器。 通过专门的测试平台可以成功进行设计验证，并通过SystemVerilog接口将其连接到提供的AHB。 top.sv顶部模块 ddr3_controller.sv ddr3内存控制器 st_defs.svh ddr3_controller.sv的参数，控制器状态 intf.sv连接ddr3_controller.sv和ddr3.v的接口 ddr3.v给定的ddr3内存 1024Mb_ddr3_parameters.vh ddr3.v的给定参数 sg093.v ddr3.v的给定参数 defs.svh ddr3.v的给定参数

一个很好的状态机学习文档，貌似是台湾人写的，不错。。。。使用verilog描述的

IAR-VisualSTATE-V623.iso为安装包，基于状态机的嵌入式系统开发最好用的工具平台，网上有很多资料可以参考。事件处理机制。安装包中还有一个200多页的开发资料。手把手教你使用。

订单及其状态机的设计实现.doc

文档为LabVIEW教程--使用 LabVIEW EE中的状态机结构实现动态复杂流程详解文档，是一份不错的参考资料，感兴趣的可以下载看看，，，，，，，，，，，，，，，

State Machine Replication is More Expensive than Consensus.pdf Consensus and State Machine Replication (SMR) are generally considered to be equivalent problems. In certain system models, indeed, the two problems are computationally equivalent: any solution to the former problem leads to a solution to the latter, and vice versa. In this paper, we study the relation between consensus and SMR from a complexity perspective.

Towards Low Latency State Machine Replication for Uncivil Wide-area Networks.pdf We consider the problem of building state machines in a multi-site environment in which there is lack of trust between sites, but not within a site. This system model recognizes the fact that if a server is attacked, then there are larger issues at play than simply masking the failure of the server. We describe the design principles of a low-latency Byzantine state machine protocol, called RAM