DSP6657+FPGA A7架构信号处理电路设计

[{"title":"（ 12 个子文件 2.06MB ） DSP6657+FPGA A7架构信号处理电路设计","children":[{"title":"XC7A200T&AD9364","children":[{"title":"01 POWER.SchDoc <span style='color:#111;'> 536.00KB </span>","children":null,"spread":false},{"title":"07 DSP DDR.SchDoc <span style='color:#111;'> 793.00KB </span>","children":null,"spread":false},{"title":"10 AD9364.SchDoc <span style='color:#111;'> 405.00KB </span>","children":null,"spread":false},{"title":"XC7A200T&AD9364.PcbDoc <span style='color:#111;'> 12.04MB </span>","children":null,"spread":false},{"title":"08 DSP POWER.SchDoc <span style='color:#111;'> 1.96MB </span>","children":null,"spread":false},{"title":"03 FPGA BANK.SchDoc <span style='color:#111;'> 1.16MB </span>","children":null,"spread":false},{"title":"05 DSP SYSTEM.SchDoc <span style='color:#111;'> 1.14MB </span>","children":null,"spread":false},{"title":"06 DSP INTERFACE.SchDoc <span style='color:#111;'> 2.38MB </span>","children":null,"spread":false},{"title":"02 PHY.SchDoc <span style='color:#111;'> 340.50KB </span>","children":null,"spread":false},{"title":"04 FPGA SYSTEM.SchDoc <span style='color:#111;'> 1.52MB </span>","children":null,"spread":false},{"title":"XC7A200T&AD9364.PrjPCB <span style='color:#111;'> 34.00KB </span>","children":null,"spread":false},{"title":"09 RF_FEED_POWER_CLK.SchDoc <span style='color:#111;'> 1.07MB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]