8 SFP Connectors 4 Transceiver Based SFPs 4 LVDS Bases SFPs • 8 SMAs 2 Transceiver Receive SMAs 2 Transceiver Transmit SMAs 1 LVDS Clock Input SMA pair (2 SMAs) 2 Single-ended Clock Outputs SMAs 1 LVDS Clock Output SMA pair (2 SMAs) 1 LVPECL Clock Output SMA pair (2 SMAs) • Power 12V to 4V 4V to 3.3V • Clocks 61.44 MHz 125 MHz 155.52 MHz 156.25 MHz Differential SMA • High Speed Mezzanine Card (HSMC)
2025-07-14 18:41:49 1.86MB hsmc altera fpga
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Stratix IV GX 开发套件HSMC_breakout_header原理图和PCB源文件,assembly、layout、schematic
2022-12-01 19:36:41 3.84MB Stratix4 FPGA Altera 开发套件
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