Cyclone10 FPGA读写MP25P16 spiflash实验Verilog源码Quartus17.1工程文件+文档资料,, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module spi_flash_top( input sys_clk, input rst, output nCS, output DCLK, output MOSI, input MISO, input[15:0] clk_div, input[3:0] cmd, input cmd_valid, output cmd_ack, input[23:0] addr, input[7:0] data_in, input[8:0] size, output data_req, output reg[7:0] data_out, output reg data_valid ); localparam S_IDLE = 0; localparam S_SE = 1; localparam S_BE = 2; localparam S_READ = 3; localparam S_WRITE = 4; localparam S_ACK = 5; localparam S_CK_STATE = 6; //present state monitor localparam S_WREN = 7; wire spi_flash_cmd_ack; reg[3:0] sub_cmd; reg sub_cmd_valid; reg[8:0] sub_size; reg[4:0] state,next_state; reg[7:0] state_reg; wire sub_data_valid; wire[7:0] sub_data_in; wire[7:0] sub_data_out; assign sub_data_in = data_in; assign cmd_ack = (state == S_ACK); always@(posedge sys_clk or posedge rst) begin if(rst==1) state <= S_IDLE; else state <= next_state; end always@(*) begin case(state) S_IDLE: if(cmd_valid && cmd == `CMD_BE) next_state <= S_WREN; else if(cmd_valid && cmd == `CMD_SE) next_state <= S_WREN; else if(cmd_valid && cmd == `CMD_READ) next_state <= S_READ; else if(cmd_valid && cmd == `CMD_PP) next_state <= S_WREN; else next_state <= S_IDLE; S_WREN: if(spi_flash_cmd_ack && cmd == `CMD_BE) next_state <= S_BE; else if(spi_flash_cmd_ack && cmd == `CMD_SE) next_state <= S_SE; else if(spi_flash_cmd_ack && cmd == `CMD_PP) next_state <= S_WRITE; else next_state <= S_WREN; S_BE: if(spi_flash_cmd_ack) next_state <= S_CK_STATE;//读取状态寄存器 else next_state <= S_BE; S_SE: if(spi_flash_cmd_ack) next_state <= S_CK_STATE;

Spartan 6 FPGA 设计经典流水灯实验VERILOG源码 Xilinx ISE14.6 工程文件 //拨码开关SW3作为开关信号，导航按键UP和DOWN作为LED流动方向控制信号，实现8个LED开关、方向可控的流水灯功能 module sp6( input ext_clk_25m, //外部输入25MHz时钟信号 input ext_rst_n, //外部输入复位信号，低电平有效 input[0:0] switch, //拨码开关SW3输入，ON -- 低电平；OFF -- 高电平 input key_upup,key_down, //up和down两个导航按键输入，未按下为高电平，按下后为低电平 output reg[7:0] led //8个LED指示灯接口 ); //------------------------------------- //按键抖动判断逻辑 wire key; //所有按键值相与的结果，用于按键触发判断 reg[3:0] keyr; //按键值key的缓存寄存器 assign key = key_upup & key_down; always @(posedge ext_clk_25m or negedge ext_rst_n) if (!ext_rst_n) keyr <= 4'b1111; else keyr <= {keyr[2:0],key}; wire key_neg = ~keyr[2] & keyr[3]; //有按键被按下 wire key_pos = keyr[2] & ~keyr[3]; //有按键被释放 //------------------------------------- //定时计数逻辑，用于对按键的消抖判断 reg[19:0] cnt; always @ (posedge ext_clk_25m or negedge ext_rst_n) if (!ext_rst_n) cnt <= 20'd0; else if(key_pos || key_neg) cnt <=20'd0; else if(cnt < 20'd999_999) cnt <= cnt + 1'b1; else cnt <= 20'd0; reg[1:0] key_value[1:0]; always @(posedge ext_clk_25m or negedge ext_rst_n) if (!ext_rst_n) begin key_value[0] <= 2'b11; key_value[1] <= 2'b11; end else if(cnt == 20'd999_999) begin //定时键值采集 key_value[0] <= {key_upup,key_down}; key_value[1] <= key_value[0]; end wire[1:0] key_press = key_value[1] & ~key_value[0]; //消抖后按键值变化标志位 //------------------------------------ //流水灯开启、停止和流动方向控制开关、按键值采集 reg led_en; //LED流水灯工作使能信号，高电平有效 reg led_dir; //LED流水灯方向控制信号，1--从高到低流动，0--从低到高流动 always @ (posedge ext_clk_25m or negedge ext_rst_n) if(!ext_rst_n) begin led_en <= 1'b0; led_dir <= 1'b0; end else begin //流水灯开启/停止控制 if(!switch[0]) led_en <= 1'b1; else led_en <= 1'b0; //流水灯方向控制 if(key_press[0]) led_dir <= 1'b0; //从低到高流动 else if(key_press[1]) led_dir <= 1'b1; //从高到低流动 else ; end //------------------------------------ //LED流水灯变化延时计数器 reg[23:0] delay; always @ (posedge ext_clk_25m or negedge ext_rst_n) if(!ext_rst_n) delay <= 24'd0; else delay <= dela

Uart串口读写实验Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module uart_test( input clk, input rst_n, input uart_rx, output uart_tx ); parameter CLK_FRE = 50;//Mhz localparam IDLE = 0; localparam SEND = 1; //send HELLO ALINX\r\n localparam WAIT = 2; //wait 1 second and send uart received data reg[7:0] tx_data; reg[7:0] tx_str; reg tx_data_valid; wire tx_data_ready; reg[7:0] tx_cnt; wire[7:0] rx_data; wire rx_data_valid; wire rx_data_ready; reg[31:0] wait_cnt; reg[3:0] state; assign rx_data_ready = 1'b1;//always can receive data, //if HELLO ALINX\r\n is being sent, the received data is discarded always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin wait_cnt <= 32'd0; tx_data <= 8'd0; state <= IDLE; tx_cnt <= 8'd0; tx_data_valid <= 1'b0; end else case(state) IDLE: state <= SEND; SEND: begin wait_cnt <= 32'd0; tx_data <= tx_str; if(tx_data_valid == 1'b1 && tx_data_ready == 1'b1 && tx_cnt < 8'd12)//Send 12 bytes data begin tx_cnt <= tx_cnt + 8'd1; //Send data counter end else if(tx_data_valid && tx_data_ready)//last byte sent is complete begin tx_cnt <= 8'd0; tx_data_valid <= 1'b0; state <= WAIT; end else if(~tx_data_valid) begin tx_data_valid <= 1'b1; end end WAIT: begin wait_cnt <= wait_cnt + 32'd1; if(rx_data_valid == 1'b1) begin tx_data_valid <= 1'b1; tx_data <= rx_data; // send uart received data end else if(tx_data_valid && tx_da

SD卡读写Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module sd_card_test( input clk, input rst_n, input key, output sd_ncs, output sd_dclk, output sd_mosi, input sd_miso, output [3:0] led ); parameter S_IDLE = 0; parameter S_READ = 1; parameter S_WRITE = 2; parameter S_END = 3; reg[3:0] state; wire sd_init_done; reg sd_sec_read; wire[31:0] sd_sec_read_addr; wire[7:0] sd_sec_read_data; wire sd_sec_read_data_valid; wire sd_sec_read_end; reg sd_sec_write; wire[31:0] sd_sec_write_addr; reg [7:0] sd_sec_write_data; wire sd_sec_write_data_req; wire sd_sec_write_end; reg[9:0] wr_cnt; reg[9:0] rd_cnt; wire button_negedge; reg[7:0] read_data; assign sd_sec_read_addr = 32'd0; assign sd_sec_write_addr = 32'd0; assign led = ~read_data[3:0]; ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key), .button_posedge (), .button_negedge (button_negedge), .button_out () ); always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_cnt <= 10'd0; else if(state == S_WRITE) begin if(sd_sec_write_data_req == 1'b1) wr_cnt <= wr_cnt + 10'd1; end else wr_cnt <= 10'd0; end always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) rd_cnt <= 10'd0; else if(state == S_READ) begin if(sd_sec_read_data_valid == 1'b1) rd_cnt <= rd_cnt + 10'd1; end else rd_cnt <= 10'd0; end always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) read_data <= 8'd0; else if(state == S_READ) begin if(sd_sec_read_data_valid == 1'b1 && rd_cnt == 10'd0) read_data <= sd_se

按键消抖实验Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料，FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module key_debounce( input clk, input rst_n, input key, output [3:0] led ); wire button_negedge; //Key falling edge ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key), .button_posedge (), .button_negedge (button_negedge), .button_out () ); wire[3:0] count; wire t0; count_m10 count10_m0( .clk (clk), .rst_n (rst_n), .en (button_negedge), .clr (1'b0), .data (count), .t (t0) ); assign led = ~count; endmodule

sdram读写测试实验Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料,FPGA为CYCLONE10LP系列中的10CL025YU256C8.SDRAMN HYNIX/海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的 TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,完整的Quartus工程文件，可以做为你的学习设计参考。 module top ( input clk, input rst_n, output[1:0] led, output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data ); parameter MEM_DATA_BITS = 16 ; //external memory user interface data width parameter ADDR_BITS = 24 ; //external memory user interface address width parameter BUSRT_BITS = 10 ; //external memory user interface burst width parameter BURST_SIZE = 128 ; //burst size wire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clock wire wr_burst_finish; // from external memory controller,burst write finish wire rd_burst_finish; // from external memory controller,burst read finish wire rd_burst_req; // to external memory controller,send out a burst read request wire wr_burst_req; // to external memory controller,send out a burst write request wire[BUSRT_BITS - 1:0] rd_burst_len; // to exter

USB2.0测速实验Cyclone10 FPGA Verilog源码Quartus17.1工程文件+文档资料，FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module top ( input clk, input ft_clk, input ft_rxf_n, //Data available input ft_txe_n, //Space available output ft_oe_n, output ft_rd_n, output ft_wr_n, inout[7:0] ft_data ); ft232h ft232h_m0 ( .ft_clk (ft_clk ), .rst (1'b0 ), .ft_rxf_n (ft_rxf_n), //Data available .ft_txe_n (ft_txe_n), //Space available .ft_oe_n (ft_oe_n ), .ft_rd_n (ft_rd_n ), .ft_wr_n (ft_wr_n ), .ft_data (ft_data ) ); module ft232h ( input ft_clk, input rst, input ft_rxf_n, //Data available input ft_txe_n, //Space available output ft_oe_n, output reg ft_rd_n, output ft_wr_n, inout[7:0] ft_data ); localparam IDLE = 0; localparam READ = 1; localparam WRITE = 2; reg[3:0] state; reg buf_wr; reg[7:0] buf_data; wire[7:0] ft_data_out; wire buf_empty; wire buf_full; wire buf_rd; reg ft_oe_n_d0; assign ft_oe_n = (state == READ) ? 1'b0 : 1'b1; assign ft_data = (ft_oe_n == 1'b0) ? 8'hzz : ft_data_out; assign ft_wr_n = (state == WRITE && ft_txe_n == 1'b0 && buf_empty == 1'b0) ? 1'b0 : 1'b1; assign buf_rd = (state == WRITE && ft_txe_n == 1'b0 && buf_empty == 1'b0) ? 1'b1 : 1'b0; ft_buf ft_buf_m0( .aclr (1'b0 ), .data (buf_data ), .rdclk (ft_clk ), .rdreq (buf_rd ), .wrclk (ft_clk ), .wrreq (buf_wr ), .q (ft_data_out ),

Spartan 6 FPGA 设计HC-SR04超声波测距实验VERILOG源码 Xilinx ISE14.6 工程文件 /每秒产生1个超声波测距模块所需的10us高脉冲激励，并用chipscope pro查看回响信号 module sp6( input ext_clk_25m, //外部输入25MHz时钟信号 input ext_rst_n, //外部输入复位信号，低电平有效 output ultrasound_trig, //超声波测距模块脉冲激励信号，10us的高脉冲 input ultrasound_echo, //超声波测距模块回响信号 output[0:0] led //D2指示灯 ); //------------------------------------- //PLL例化 wire clk_12m5; //PLL输出12.5MHz时钟 wire clk_25m; //PLL输出25MHz时钟 wire clk_50m; //PLL输出50MHz时钟 wire clk_100m; //PLL输出100MHz时钟 wire sys_rst_n; //PLL输出的locked信号，作为FPGA内部的复位信号，低电平复位，高电平正常工作 pll_controller uut_pll_controller (// Clock in ports .CLK_IN1(ext_clk_25m), // IN // Clock out ports .CLK_OUT1(clk_12m5), // OUT .CLK_OUT2(clk_25m), // OUT .CLK_OUT3(clk_50m), // OUT .CLK_OUT4(clk_100m), // OUT // Status and control signals .RESET(~ext_rst_n),// IN .LOCKED(sys_rst_n)); // OUT //------------------------------------- //25MHz时钟进行分频，产生一个100KHz频率的时钟使能信号 wire clk_100khz_en; //100KHz频率的一个时钟使能信号，即每10us产生一个时钟脉冲 clkdiv_generation uut_clkdiv_generation( .clk(clk_25m), //时钟信号 .rst_n(sys_rst_n), //复位信号，低电平有效 .clk_100khz_en(clk_100khz_en) //100KHz频率的一个时钟使能信号，即每10us产生一个时钟脉冲 ); //------------------------------------- //每秒产生一个10us的高脉冲作为超声波测距模块的激励 ultrasound_controller uut_ultrasound_controller( .clk(clk_25m), //时钟信号 .rst_n(sys_rst_n), //复位信号，低电平有效 .clk_100khz_en(clk_100khz_en), //100KHz频率的一个时钟使能信号，即每10us产生一个时钟脉冲 .ultrasound_trig(ultrasound_trig), //超声波测距模块脉冲激励信号，10us的高脉冲 .ultrasound_echo(ultrasound_echo) //超声波测距模块回响信号 ); //------------------------------------- //input信号必须经过IBUF后，才能作为chipscope中查看 wire ultrasound_echo_r; IBUF #( .IOSTANDARD("DEFAULT") // Specify the input I/O standard )IBUF_inst ( .O(ultrasound_echo_r), // Buffer output .I(ultrasound_echo) // Buffer input (connect directly to top-level port) ); assign led[0] = ultrasound_echo_

从零开始设计一个CPU （Verilog） 版本 V1.0 vivado 2019.2 ========================= 资源 B站 视频地址： 作业说明（包括指令设计和模块结构） 版权问题不再提供下载： 源码（未打包）： 打包工程（vivado打开即用）： 参考讲义 版权问题不再提供下载： 汇编程序 给定一个非零自然数N，计算小于N的自然数之和 0000100011 //0// READ INPUT TO R3 1000000001 //1// INIT R0 = 1 1010000000 //2// INIT R1 = 0 0100010100 //3// R1 = R0 + R1 0010000001 //4// R0 = R0 + 1 0001110011 //5// IF R0 < R3 THEN Z = 0 ELSE Z = 1 0001010011 //6/

通过按键输入学号，并循环显示：电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。