EPM240 CPLD开发板Verilog HDL设计实验例程15例Quartus 13.1工程+设计说明文档，例程如下：
ex10_iic
ex11_sram
ex12_kz
ex13_maxiiclk
ex14_maxiiufm
ex15_sim
ex1_clkdiv
ex2_key
ex3_johnson
ex4_seg7
ex5_mux
ex6_module
ex7_vga
ex8_232
ex9_ps2
2021-03-31 16:08:05
7.64MB