dnn-RTL
 USC DNN系统的RTL和FPGA实现-Sourya,Yinan,Chiye,Mahdi
 testbench-主文件是tb_mnist.v。 其他文件用于婴儿网络或子模块。
 src-所有源代码Verilog文件。 等级制度:
 DNN.v	-	whole network
layer_block.v	-	Contains processors, memory, state machines and other small logic for each layer
memory_ctr.v	-	State machine for each layer. Generates control signals for memory (address, enable), counter and mux
processor_set.v	-	FF, BP and UP proces
                                    
                                    
                                        
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