以太网EMAC IP核，verilog hdl语言源码，内含所有源码和测试代码，说明文档。

附带源码！！根据全自动洗衣机的控制原理设计一个控制电路，使之能够控制全自动洗衣机完成整个工作过程。

高等学校电子信息类专业系列教材 EDA原理及Verilog HDL实现 从晶体管、门电路到Xilinx Vivado的数字系统设计

该文档里包含verilog语言编写的双线性插值实现图像缩放的算法

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still make it difficult to properly synthesize and analyze the design. This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #1) is included.

Verilog HDL实现了使用WM8731对音频进行采样，并且使用ALTERA FPGA实现了频谱计算（FFT），在VGA上显示频谱