适合51单片机初学者的一些汇编实例，包括按键，键盘扫描，定时器，led,lcd1602,8位数码管，步进电机，红外显示等应用实例
2022-03-01 11:49:49
166KB
1
Multisim14电子系统仿真与设计-Multisim实验例程源文件（78个），可以做为你的学习实验参考。
2022-02-14 14:05:52
9.92MB
verilog语言程序实例实验例程源码（120例）:
acc.v
accn.v
account.v
add4_1.v
add4_2.v
add4_3.v
add8.v
add8_tp.v
adder.v
adder16.v
adder4.acf
adder4.hif
adder4.ndb
adder4.v
adder8.v
adder_tp.v
add_ahead.v
add_bx.v
add_jl.v
add_tree.v
alu.v
alutask.v
alu_tp.v
aoi.v
bidir.v
bidir2.v
block.v
block1.v
block2.v
block3.v
block4.v
buried_ff.v
carry_udp.v
carry_udpx1.v
carry_udpx2.v
clock.v
code_83.v
compile.v
control.v
correlator.v
count.v
count10.v
count4.v
count4_tp.v
count60.v
count8_tp.v
crc.v
cycle.v
decode47.v
decode4_7.v
decoder1.v
decoder2.v
decoder_38.v
delay.v
dff.v
dff1.v
dff2.v
dff_udp.v
encoder8_3.v
examples.pdf
fir.v
fre_ctrl.v
fsm.v
full_add1.v
full_add2.v
full_add3.v
full_add4.v
full_add5.v
funct.v
funct_tp.v
gate1.v
gate2.v
gate3.v
half_add1.v
half_add2.v
half_add3.v
half_add4.v
jk_ff.v
johnson.v
latch.v
latch_1.v
latch_16.v
latch_2.v
latch_8.v
linear.v
longframe1.v
longframe2.v
loop1.v
loop2.v
loop3.v
mac.v
mac_tp.v
map_lpm_ram.v
mpc.v
mpc_tp.v
mult.v
mult4x4.v
mult_for.v
mult_repeat.v
mult_tp.v
mux21_1.v
mux21_2.v
mux2_1a.v
mux2_1b.v
mux2_1c.v
mux31.v
mux4_1.v
mux4_1a.v
mux4_1b.v
mux4_1c.v
mux4_1d.v
mux_case.v
mux_casez.v
mux_if.v
mux_tp.v
non_block.v
paobiao.v
paral1.v
paral2.v
parity.v
pipeline.v
ram256x8.v
random_tp.v
reg8.v
resource1.v
resource2.v
rom.v
sell.v
serial1.v
serial2.v
serial_pal.v
shifter.v
song.v
test.v
test1.v
2021-12-11 21:02:07
165KB
初学者非常实用的例程代码，增加对单片机的学习理解，从引脚控制的原理方面有很大的帮助，本人从事嵌入式开发工作最开始学习的一个例程之一
2021-12-11 14:44:00
279KB
1
飓风cyclone FPGA开发板verilog逻辑例程Quartus工程源码文件（16例）：
low_cost_lcd
S1_38yima
S2_div
S3_WAVE
S4_LCD_V
S4_LCD_VHDL
S5_UART
S6_VGA
S6_VGA_change
S7_PS2_LCD
S7_PS2_RS232
S8_test
T1_SW_PB
T2_USB_IN
T3_USB_OUT
T4_LED_RUN
1。源文件保存在src目录，QII的工程文件保存在Proj目录；
2。程序可以在VGA显示器上以800x600分辨率显示方波示例和字母示例
3。具体设计参考代码。
`timescale 1ns/1ns
module UART_tb;
wire tbre;
wire tsre;
wire sdo ;
wire rxd;
reg [7:0] din;
reg rst ;
reg clk16x ;
reg wrn;
reg rdn;
wire [7:0] dout;
wire data_ready;
wire framing_error ;
wire parity_error ;
uart PC (.dout(dout),
.data_ready(data_ready),
.framing_error(framing_error),
.parity_error(parity_error),
.rxd(rxd),
.clk16x(clk16x),
.rst(rst),
.rdn(rdn),
.din(din),
.tbre(tbre),
.tsre(tsre),
.wrn(wrn),
.sdo(sdo)
) ;
uart_if FPGA (.clk(clk16x),
.rst_n(~rst),
.txd(rxd),
.rxd(sdo)
);
// Enter fixture code here
initial begin
din = 0;
rst = 0;
clk16x = 0;
wrn = 1;
rdn = 1;
end
always #10 clk16x = ~clk16x ;
initial begin
#3 rst = 1'b1 ;
din ="R";// 8'b11110000 ;
#5000 rst = 1'b0 ;
#30 wrn = 1'b0 ;
#150 wrn = 1'b1 ;
//#4000 din ="r"; // 8'b10101010 ;
//#870 wrn = 1'b0 ;
//#200 wrn = 1'b1 ;
#104000 din ="r"; // 8'b10101010 ;
#870 wrn = 1'b0 ;
#200 wrn = 1'b1 ;
#104000 $stop;
end
always @(posedge data_ready)
begin
#100 rdn=0;
#500 rdn=1;
end
endmodule // Uart_tb
2021-12-02 17:05:02
54.74MB