Verilog HDL描述的8051内核源代码

[{"title":"（ 38 个子文件 54KB ） Verilog HDL描述的8051内核源代码","children":[{"title":"Verilog描述的8051","children":[{"title":"使用说明请参看右侧注释===〉〉.txt <span style='color:#111;'> 771B </span>","children":null,"spread":false},{"title":"8051core-Verilog","children":[{"title":"Ram_sel.v <span style='color:#111;'> 4.41KB </span>","children":null,"spread":false},{"title":"Sp.v <span style='color:#111;'> 3.93KB </span>","children":null,"spread":false},{"title":"Defines.v <span style='color:#111;'> 14.10KB </span>","children":null,"spread":false},{"title":"op_select.v <span style='color:#111;'> 5.44KB </span>","children":null,"spread":false},{"title":"Psw.v <span style='color:#111;'> 4.80KB </span>","children":null,"spread":false},{"title":"Reg2.v <span style='color:#111;'> 3.06KB </span>","children":null,"spread":false},{"title":"Multiply.v <span style='color:#111;'> 2.29KB </span>","children":null,"spread":false},{"title":"Acc.v <span style='color:#111;'> 4.19KB </span>","children":null,"spread":false},{"title":"alu_src1_sel.v <span style='color:#111;'> 3.58KB </span>","children":null,"spread":false},{"title":"Reg4.v <span style='color:#111;'> 3.06KB </span>","children":null,"spread":false},{"title":"IndiAddr.v <span style='color:#111;'> 4.52KB </span>","children":null,"spread":false},{"title":"Make <span style='color:#111;'> 322B </span>","children":null,"spread":false},{"title":"Reg5.v <span style='color:#111;'> 3.06KB </span>","children":null,"spread":false},{"title":"Pc.v <span style='color:#111;'> 7.83KB </span>","children":null,"spread":false},{"title":"alu_src2_sel.v <span style='color:#111;'> 3.42KB </span>","children":null,"spread":false},{"title":"alu_src3_sel.v <span style='color:#111;'> 3.23KB </span>","children":null,"spread":false},{"title":"transcript <span style='color:#111;'> 251B </span>","children":null,"spread":false},{"title":"Rom.v <span style='color:#111;'> 14.00KB </span>","children":null,"spread":false},{"title":"Decoder.v <span style='color:#111;'> 82.67KB </span>","children":null,"spread":false},{"title":"Divide.v <span style='color:#111;'> 4.56KB </span>","children":null,"spread":false},{"title":"Reg8.v <span style='color:#111;'> 3.11KB </span>","children":null,"spread":false},{"title":"cy_select.v <span style='color:#111;'> 3.45KB </span>","children":null,"spread":false},{"title":"Alu.v <span style='color:#111;'> 7.32KB </span>","children":null,"spread":false},{"title":"ram_rd_sel.v <span style='color:#111;'> 3.50KB </span>","children":null,"spread":false},{"title":"Reg3.v <span style='color:#111;'> 3.06KB </span>","children":null,"spread":false},{"title":"Comp.v <span style='color:#111;'> 3.67KB </span>","children":null,"spread":false},{"title":"Dptr.v <span style='color:#111;'> 3.91KB </span>","children":null,"spread":false},{"title":"Ram.v <span style='color:#111;'> 6.40KB </span>","children":null,"spread":false},{"title":"Port_out.v <span style='color:#111;'> 4.17KB </span>","children":null,"spread":false},{"title":"immediate_sel.v <span style='color:#111;'> 3.50KB </span>","children":null,"spread":false},{"title":"All.v <span style='color:#111;'> 12.18KB </span>","children":null,"spread":false},{"title":"rom_addr_sel.v <span style='color:#111;'> 3.80KB </span>","children":null,"spread":false},{"title":"Reg8r.v <span style='color:#111;'> 3.18KB </span>","children":null,"spread":false},{"title":"Reg1.v <span style='color:#111;'> 3.04KB </span>","children":null,"spread":false},{"title":"ram_wr_sel.v <span style='color:#111;'> 3.63KB </span>","children":null,"spread":false},{"title":"Tb_all.v <span style='color:#111;'> 4.04KB </span>","children":null,"spread":false},{"title":"ext_addr_sel.v <span style='color:#111;'> 3.49KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}]