ethernet_tri_mode的Verilog代码

[{"title":"（ 37 个子文件 29KB ） ethernet_tri_mode的Verilog代码","children":[{"title":"ethernet_tri_mode","children":[{"title":"Phy_int.v <span style='color:#111;'> 8.31KB </span>","children":null,"spread":false},{"title":"afifo.v <span style='color:#111;'> 6.27KB </span>","children":null,"spread":false},{"title":"MAC_tx.v <span style='color:#111;'> 12.79KB </span>","children":null,"spread":false},{"title":"RMON","children":[{"title":"RMON_addr_gen.v <span style='color:#111;'> 11.09KB </span>","children":null,"spread":false},{"title":"RMON_ctrl.v <span style='color:#111;'> 9.86KB </span>","children":null,"spread":false},{"title":"RMON_dpram.v <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false}],"spread":true},{"title":"MAC_top.v <span style='color:#111;'> 22.26KB </span>","children":null,"spread":false},{"title":"reg_int.v <span style='color:#111;'> 9.99KB </span>","children":null,"spread":false},{"title":"eth_miim.v <span style='color:#111;'> 16.24KB </span>","children":null,"spread":false},{"title":"MAC_rx.v <span style='color:#111;'> 11.84KB </span>","children":null,"spread":false},{"title":"RMON.v <span style='color:#111;'> 9.01KB </span>","children":null,"spread":false},{"title":"MAC_rx","children":[{"title":"MAC_rx_add_chk.v <span style='color:#111;'> 6.58KB </span>","children":null,"spread":false},{"title":"Broadcast_filter.v <span style='color:#111;'> 5.02KB </span>","children":null,"spread":false},{"title":"MAC_rx_ctrl.v <span style='color:#111;'> 21.78KB </span>","children":null,"spread":false},{"title":"CRC_chk.v <span style='color:#111;'> 6.07KB </span>","children":null,"spread":false},{"title":"MAC_rx_FF.v <span style='color:#111;'> 25.42KB </span>","children":null,"spread":false}],"spread":true},{"title":"Clk_ctrl.v <span style='color:#111;'> 5.12KB </span>","children":null,"spread":false},{"title":"MAC_tx","children":[{"title":"Ramdon_gen.v <span style='color:#111;'> 5.41KB </span>","children":null,"spread":false},{"title":"MAC_tx_Ctrl.v <span style='color:#111;'> 22.45KB </span>","children":null,"spread":false},{"title":"flow_ctrl.v <span style='color:#111;'> 7.58KB </span>","children":null,"spread":false},{"title":"CRC_gen.v <span style='color:#111;'> 7.10KB </span>","children":null,"spread":false},{"title":"MAC_tx_FF.v <span style='color:#111;'> 25.82KB </span>","children":null,"spread":false},{"title":"MAC_tx_addr_add.v <span style='color:#111;'> 5.72KB </span>","children":null,"spread":false}],"spread":true},{"title":"miim","children":[{"title":"eth_shiftreg.v <span style='color:#111;'> 6.68KB </span>","children":null,"spread":false},{"title":"timescale.v <span style='color:#111;'> 3.08KB </span>","children":null,"spread":false},{"title":"eth_outputcontrol.v <span style='color:#111;'> 6.26KB </span>","children":null,"spread":false},{"title":"eth_clockgen.v <span style='color:#111;'> 5.47KB </span>","children":null,"spread":false}],"spread":true},{"title":"TECH","children":[{"title":"CLK_DIV2.v <span style='color:#111;'> 3.45KB </span>","children":null,"spread":false},{"title":"CLK_SWITCH.v <span style='color:#111;'> 3.38KB </span>","children":null,"spread":false},{"title":"xilinx","children":[{"title":"CLK_DIV2.v <span style='color:#111;'> 3.51KB </span>","children":null,"spread":false},{"title":"CLK_SWITCH.v <span style='color:#111;'> 3.58KB </span>","children":null,"spread":false},{"title":"duram.v <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false}],"spread":false},{"title":"altera","children":[{"title":"CLK_DIV2.v <span style='color:#111;'> 3.51KB </span>","children":null,"spread":false},{"title":"CLK_SWITCH.v <span style='color:#111;'> 3.45KB </span>","children":null,"spread":false},{"title":"duram.v <span style='color:#111;'> 2.35KB </span>","children":null,"spread":false}],"spread":false},{"title":"duram.v <span style='color:#111;'> 2.35KB </span>","children":null,"spread":false}],"spread":false},{"title":"header.v <span style='color:#111;'> 190B </span>","children":null,"spread":false}],"spread":false}],"spread":true}]