ic前端经典书籍

[{"title":"（ 10 个子文件 47MB ） ic前端经典书籍","children":[{"title":"经典中的经典！ic前端几本经典书籍（五本书全部到齐！！）","children":[{"title":"1","children":[{"title":"详细讲述了在IC DESIGN FLOW中.txt <span style='color:#111;'> 180B </span>","children":null,"spread":false},{"title":"(Kluwer) Principles of Verifiable RTL Design (2nd Ed.).pdf <span style='color:#111;'> 3.94MB </span>","children":null,"spread":false}],"spread":true},{"title":"5","children":[{"title":"Reuse.Methodology.Manual.3rd.Edition.pdf <span style='color:#111;'> 6.42MB </span>","children":null,"spread":false},{"title":"新建 文本文档.txt <span style='color:#111;'> 155B </span>","children":null,"spread":false}],"spread":true},{"title":"2","children":[{"title":"新建 文本文档.txt <span style='color:#111;'> 215B </span>","children":null,"spread":false},{"title":"(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf <span style='color:#111;'> 5.69MB </span>","children":null,"spread":false}],"spread":true},{"title":"3","children":[{"title":"新建 文本文档.txt <span style='color:#111;'> 162B </span>","children":null,"spread":false},{"title":"A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.pdf <span style='color:#111;'> 38.75MB </span>","children":null,"spread":false}],"spread":true},{"title":"4","children":[{"title":"Advanced.ASIC.Chip.Synthesis.2nd.Edition.pdf <span style='color:#111;'> 15.23MB </span>","children":null,"spread":false},{"title":"新建 文本文档.txt <span style='color:#111;'> 251B </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]