01_FSM_welcome.rar

[{"title":"（ 83 个子文件 166KB ） 01_FSM_welcome.rar","children":[{"title":"01_FSM_welcome","children":[{"title":"IP","children":null,"spread":false},{"title":"RTL","children":[{"title":"FSM_welcome.v.bak <span style='color:#111;'> 128B </span>","children":null,"spread":false},{"title":"FSM_welcome.v <span style='color:#111;'> 2.40KB </span>","children":null,"spread":false}],"spread":true},{"title":"testbench","children":[{"title":"FSM_welcome_tb.v.bak <span style='color:#111;'> 84B </span>","children":null,"spread":false},{"title":"FSM_welcome_tb.v <span style='color:#111;'> 982B </span>","children":null,"spread":false}],"spread":true},{"title":"doc","children":null,"spread":false},{"title":"project","children":[{"title":"FSM_welcome.qws <span style='color:#111;'> 2.14KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"FSM_welcome.sgate_sm.nvd <span style='color:#111;'> 2.50KB </span>","children":null,"spread":false},{"title":"FSM_welcome.sgdiff.hdb <span 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</span>","children":null,"spread":false},{"title":"FSM_welcome.qpf <span style='color:#111;'> 1.25KB </span>","children":null,"spread":false},{"title":"simulation","children":[{"title":"modelsim","children":[{"title":"msim_transcript <span style='color:#111;'> 2.13KB </span>","children":null,"spread":false},{"title":"FSM_welcome_run_msim_rtl_verilog.do.bak1 <span style='color:#111;'> 656B </span>","children":null,"spread":false},{"title":"rtl_work","children":[{"title":"@f@s@m_welcome_tb","children":[{"title":"_primary.dbs <span style='color:#111;'> 1.62KB </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 9.60KB </span>","children":null,"spread":false},{"title":"verilog.prw <span style='color:#111;'> 801B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 88B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.01KB 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style='color:#111;'> 656B </span>","children":null,"spread":false},{"title":"FSM_welcome_run_msim_rtl_verilog.do.bak <span style='color:#111;'> 656B </span>","children":null,"spread":false},{"title":"modelsim.ini <span style='color:#111;'> 10.87KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"FSM_welcome_nativelink_simulation.rpt <span style='color:#111;'> 994B </span>","children":null,"spread":false},{"title":"output_files","children":[{"title":"FSM_welcome.map.summary <span style='color:#111;'> 476B </span>","children":null,"spread":false},{"title":"FSM_welcome.map.rpt <span style='color:#111;'> 24.08KB </span>","children":null,"spread":false},{"title":"FSM_welcome.flow.rpt <span style='color:#111;'> 8.17KB </span>","children":null,"spread":false},{"title":"FSM_welcome.done <span style='color:#111;'> 26B </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true}]