基于FPGA的_HDMI_display_controller_基于FPGA的HDMI显示控制_

[{"title":"（ 27 个子文件 115KB ） 基于FPGA的_HDMI_display_controller_基于FPGA的HDMI显示控制_","children":[{"title":"FPGA-HDMI-main","children":[{"title":"SIM","children":[{"title":"tb_clkgen.v <span style='color:#111;'> 876B </span>","children":null,"spread":false},{"title":"tb_tmds_decode.v <span style='color:#111;'> 2.74KB </span>","children":null,"spread":false},{"title":"tb_hdmi_tx_top.v <span style='color:#111;'> 6.38KB </span>","children":null,"spread":false},{"title":"pixel_generate.v <span style='color:#111;'> 2.48KB </span>","children":null,"spread":false},{"title":"tb_pixel_verify.v <span style='color:#111;'> 1.82KB </span>","children":null,"spread":false},{"title":"tb_run_iverilog.bat <span style='color:#111;'> 124B </span>","children":null,"spread":false}],"spread":true},{"title":"LICENSE <span style='color:#111;'> 34.98KB </span>","children":null,"spread":false},{"title":"RTL","children":[{"title":"hdmi_tddr.v <span style='color:#111;'> 625B </span>","children":null,"spread":false},{"title":"hdmi_tmds_encode.v <span style='color:#111;'> 5.19KB </span>","children":null,"spread":false},{"title":"hdmi_tx_top.v <span style='color:#111;'> 13.44KB </span>","children":null,"spread":false},{"title":"hdmi_async_fifo.v <span style='color:#111;'> 3.83KB </span>","children":null,"spread":false}],"spread":true},{"title":"fpga_example","children":[{"title":"hdmi.gprj.user <span style='color:#111;'> 2.72KB </span>","children":null,"spread":false},{"title":"top.cst <span style='color:#111;'> 886B </span>","children":null,"spread":false},{"title":"hdmi.gprj <span style='color:#111;'> 903B </span>","children":null,"spread":false},{"title":"top.sdc <span style='color:#111;'> 202B </span>","children":null,"spread":false},{"title":"RTL","children":[{"title":"fpga_top.v <span style='color:#111;'> 3.20KB </span>","children":null,"spread":false},{"title":"pixel_generate.v <span style='color:#111;'> 2.48KB </span>","children":null,"spread":false},{"title":"gowin_pllvr","children":[{"title":"gowin_pllvr_tmp.v <span style='color:#111;'> 618B </span>","children":null,"spread":false},{"title":"gowin_pllvr.ipc <span style='color:#111;'> 405B </span>","children":null,"spread":false},{"title":"gowin_pllvr.mod <span style='color:#111;'> 653B </span>","children":null,"spread":false},{"title":"gowin_pllvr.v <span style='color:#111;'> 1.95KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"readme.txt <span style='color:#111;'> 125B </span>","children":null,"spread":false}],"spread":true},{"title":"document","children":[{"title":"simulation_diagram.png <span style='color:#111;'> 20.63KB </span>","children":null,"spread":false},{"title":"hardware_connection.png <span style='color:#111;'> 25.59KB </span>","children":null,"spread":false},{"title":"diagram.png <span style='color:#111;'> 19.96KB </span>","children":null,"spread":false},{"title":"fpga_example_diagram.png <span style='color:#111;'> 19.75KB </span>","children":null,"spread":false}],"spread":true},{"title":"README.md <span style='color:#111;'> 10.19KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]