[{"title":"( 14 个子文件 4.42MB ) SRIO规范rev2.1","children":[{"title":"SRIO规范rev2.1_spec_stack","children":[{"title":"Part7-System and Device.pdf <span style='color:#111;'> 382.86KB </span>","children":null,"spread":false},{"title":"Part8-Error Management.pdf <span style='color:#111;'> 232.36KB </span>","children":null,"spread":false},{"title":"Part9-Flow Control Logical Layer.pdf <span style='color:#111;'> 195.44KB </span>","children":null,"spread":false},{"title":"Annex1.pdf <span style='color:#111;'> 258.68KB </span>","children":null,"spread":false},{"title":"Part2-Message Passing Logical.pdf <span style='color:#111;'> 278.29KB </span>","children":null,"spread":false},{"title":"Part3-Common Transport.pdf <span style='color:#111;'> 147.85KB </span>","children":null,"spread":false},{"title":"Part6-LP-Serial Physical.pdf <span style='color:#111;'> 2.18MB </span>","children":null,"spread":false},{"title":"Part5-Globally Shared Memory.pdf <span style='color:#111;'> 911.17KB </span>","children":null,"spread":false},{"title":"Part11-Multicast Extensions.pdf <span style='color:#111;'> 193.16KB </span>","children":null,"spread":false},{"title":"Annex2.pdf <span style='color:#111;'> 383.70KB </span>","children":null,"spread":false},{"title":"Part1-InputOutput Logical.pdf <span style='color:#111;'> 359.04KB </span>","children":null,"spread":false},{"title":"Part12-Virtual Output Queueing.pdf <span style='color:#111;'> 124.83KB </span>","children":null,"spread":false},{"title":"Part4-Physical Layer 816.pdf <span style='color:#111;'> 1.00MB </span>","children":null,"spread":false},{"title":"Part10-Data Streaming Logical.pdf <span style='color:#111;'> 332.51KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]