[{"title":"( 4 个子文件 656KB ) 几个usb2.0 IP核","children":[{"title":"几个usb2.0 IP核","children":[{"title":"VHDL实现的USB IP核.rar <span style='color:#111;'> 147.37KB </span>","children":null,"spread":false},{"title":"VERILOG-USB2.0IP-core.rar <span style='color:#111;'> 214.99KB </span>","children":null,"spread":false},{"title":"USB2.0的IP CORE,可以直接用在SOPC下,自动完成全部的枚举,只需修改枚举参数即可.rar <span style='color:#111;'> 163.15KB </span>","children":null,"spread":false},{"title":"OpenCore 的 USB2.0 IP.rar <span style='color:#111;'> 191.89KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]