[{"title":"( 5 个子文件 2.41MB ) 超低温漂带隙基准电路设计:基于Cadence的高PSRR低功耗实现及其应用","children":[{"title":"超低温漂带隙基准电路设计文档:含推导与调试过程、仿真设置及工艺库打包.html <span style='color:#111;'> 6.77MB </span>","children":null,"spread":false},{"title":"关键技术.docx <span style='color:#111;'> 37.65KB </span>","children":null,"spread":false},{"title":"超低温漂带隙基准电路设计:基于Cadence的高PSRR低功耗实现及其应用.pdf <span style='color:#111;'> 128.02KB </span>","children":null,"spread":false},{"title":"Cadence","children":[{"title":"超低温漂带隙基准电路设计:高电源抑制比、低功耗及详细设计文档PDF.txt <span style='color:#111;'> 2.70KB </span>","children":null,"spread":false}],"spread":true},{"title":"超低温漂带隙基准电路设计:高电源抑制比、低功耗及详细设计文档PDF.docx <span style='color:#111;'> 37.59KB </span>","children":null,"spread":false}],"spread":true}]