Table of Contents Articles Introduction 0 Cookbook/Introduction 0 Cookbook/Acknowledgements 1 Testbench Architecture 2 Testbench 2 Testbench/Build 9 Testbench/Blocklevel 19 Testbench/IntegrationLevel 29 Component 39 Agent 42 Phasing 48 Factory 53 UsingFactoryOverrides 56 SystemVerilogPackages 62 Connections to DUT Interfaces 65 Connections 65 SVCreationOrder 71 Connect/SystemVerilogTechniques 73 ParameterizedTests 75 Connect/Virtual Interface 78 Config/VirtInterfaceConfigDb 86 Connect/VirtInterfacePackage 90 Connect/VirtInterfaceConfigPkg 93 Connect/TwoKingdomsFactory 97 DualTop 103 VirtInterfaceFunctionCallChain 106 BusFunctionalModels 108 ProtocolModules 111 Connect/AbstractConcrete 115 Connect/AbstractConcreteConfigDB 118 Configuring a Test Environment 126 Configuration 126 Resources/config db 131 Config/Params Package 134 Config/ConfiguringSequences 139 ResourceAccessForSequences 142 MacroCostBenefit 145 Analysis Components & Techniques 146 Analysis 146 AnalysisPort 149 AnalysisConnections 152 MonitorComponent 158 Predictors 161 Scoreboards 163 MetricAnalyzers 170 PostRunPhases 172 Matlab/Integration 175 End Of Test Mechanisms 183 EndOfTest 183 Objections 185 Sequences 188 Sequences 188 Sequences/Items 193 Transaction/Methods 195 Sequences/API 200 Connect/Sequencer 204 Driver/Sequence API 206 Sequences/Generation 213 Sequences/Overrides 221 Sequences/Virtual 223 Sequences/VirtualSequencer 231 Sequences/Hierarchy 237 Sequences/SequenceLibrary 242 Driver/Use Models 246 Driver/Unidirectional 247 Driver/Bidirectional 250 Driver/Pipelined 255 Sequences/Arbitration 267 Sequences/Priority 276 Sequences/LockGrab 277 Sequences/Slave 284 Stimulus/Signal Wait 290 Stimulus/Interrupts 294 Sequences/Stopping 301 Sequences/Layering 302 Register Abstraction Layer 308 Registers 308 Registers/Specification 315 Registers/Adapter 317 Registers/Integrating 321 Registers/Integration 327 Registers/RegisterModelOverview 332 Registers/ModelStructure 334 Registers/QuirkyRegisters 344 Reg