verilog 数字系统设计 -RTL综合 测试平台与验证(第二版)书中 源代码 从学校图书馆借的原书cd直接拷贝的 电子工业出版社
2022-03-11 22:31:01 375KB verilog rtl synthesis testbench
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RTL8201BL数据手册(中文版)
2022-03-08 21:10:28 779KB RTL8201BL RTL数据手册 (中文版)
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verilog数字系统设计-rtl综合测试平台与验证 书中的源代码 希望对大家有帮助
2022-03-07 16:30:43 464KB fpga verilog
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Over 60 hands-on recipes to help you master the power of Delphi for cross-platform and mobile development on multiple platforms. 本书包含完整的书签,方便阅读。
2022-02-28 16:02:57 7.9MB Delphi RTL 跨平台 FireMonkey
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RTL_DTL_TTL_CTL_ECL_CMOS等数字电路的定义及区别
2022-02-22 10:03:25 301KB 数字电路
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RTL2Booksim “将RTL设计连接到灵活的NoC仿真器” 该工具允许将C / C ++模拟器或RTL(Verilog)设计连接到Booksim(Booksim是斯坦福大学开发的一种广泛使用的具有周期精度的NoC模拟器,也可以在GitHub上找到)。 简而言之,RTL2Booksim允许您在Verilog设计中使用NoC,而无需实际为其编写Verilog,相反,我们使用Booksim尝试了许多不同的NoC变体,而无需额外的设计工作。 首先,请看示例。 cpp_example:调用“ send_flit”和“ send_credit”之类的函数来演示如何编写与Bookim通信的简单cpp模拟器。 verilog_example:实例化“ rtl_interface.sv”,它基本上是Booksim NoC的verilog包装器。 然后,您可以通过rtl_interface将设
2022-02-15 16:13:59 304KB C++
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RTL Design Style Guide for Verilog HDL The RTL Design Style Guide, Second Edition RTL Design Style Guide, Second Edition, reflects the advances in design environments that , reflects the advances in design environments that have been made since the 2003 publication of the first edition. The second edition introduces design have been made since the 2003 publication of the first edition. The second edition introduces design practices suitable for designs that are getting ever faster and larger. Major additions and changes practices suitable for designs that are getting ever faster and larger. Major additions and changes are as follows: are as follows:
2022-02-10 11:06:15 7.12MB RTL Verilog HDL
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RV1109_RV1126 AI人工智能视觉开发板Cadence原理图,DSN设计文件+RV1109_RV1126_RK809_RTL8211F芯片技术手册,硬件参考设计原理图及主要器件DATAsheet。
学习risc-v和axi总线的可下载
2022-01-14 14:10:44 4.69MB risc-v axi verilog cpu
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睿普康PHY芯片,以太网百兆PHY芯片,RPC8201,以太网千兆PHY芯片,RPC8211,国产PHY芯片,替换瑞昱的RTL8201,RTL8211,裕太微YT8512和YT8531,TI的DP83822
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