1800-2009 - IEEE SystemVerilog 语言标准

1800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language (Active) IEEE标准1800-2009，是2009年发布的SystemVerilog语言标准。目前该标准的状态是Active。 This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document. 该标准代表了先前两个标准的合并：IEEE Std 1364™-2005 Verilog硬件描述语言（HDL）和IEEE Std 1800-2005 SystemVerilog统一的硬件设计，规范和验证语言。 2005 SystemVerilog标准定义了对2005 Verilog标准的扩展。 这两个标准旨在用作一种语言。 将基本的Verilog语言和SystemVerilog扩展合并为一个标准，可为用户提供有关单个文档中语法和语义的所有信息。