verilog 写的单个与门以及testbench

[{"title":"（ 5 个子文件 12KB ） verilog 写的单个与门以及testbench","children":[{"title":"sim","children":[{"title":"and_gate_tb.v <span style='color:#111;'> 362B </span>","children":null,"spread":false},{"title":"and_gate_tb.v.bak <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"__Previews","children":[{"title":"and_gate_tb.vPreview <span style='color:#111;'> 20.21KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"src","children":[{"title":"and_gate.v <span style='color:#111;'> 516B </span>","children":null,"spread":false},{"title":"and_gate.v.bak <span style='color:#111;'> 517B </span>","children":null,"spread":false}],"spread":true}],"spread":true}]