//该模块为8分频器
module div8(
clk,
divout); //端口列表
input clk;
output divout; //端口说明
reg [2:0]div;
reg divout; //定义数据类型
initial
divout=0; //初始化
always @(posedge clk)
begin
div=div+1;
divout=div[2]; //3bit计数器，实现8分频
2019-12-21 21:11:50
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