chip bumping technology

Power Distribution Networks with On-Chip Decoupling Capacitors, 2nd edition is dedicated to distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. This book provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors. The book provides insight and intuition into the behavior and design of on-chip power distribution systems. This book has four primary objectives. The first objective is to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the terminals of the on-chip circuitry. The second objective is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. The third objective is to present design methodologies for efficiently placing on-chip decoupling capacitors in nanoscale integrated circuits. Finally, the fourth objective is to suggest novel architectures for distributing power across an integrated circuit, as well as provide new methodologies to efficiently analyze and design on-chip power grids. Organized into subareas to provide a more intuitive flow to the reader, this edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

经典书籍，学习研究体系结构的兄弟们必看！！

Rocket是一款64bit的标量处理器，5级流水线，采用的是risc-v指令集，集成FPU，并有许多or1200没有的特性，比如：无阻塞缓存、分支预测、返回地址堆栈、硬件页表填充、cache支持ECC、支持多核等 文档是rocket-chip的架构说明

Xilinx ZYNQ Ultrascale + ZCU102上的RISC-V火箭芯片 关于这个仓库 这是FPGA 上RISC-V的ZCU102端口。 ZCU102至少可以容纳四芯RISC-V核火箭芯片。 该存储库的火箭芯片版本与原始存储库相同，该原始存储库在2018年4月。 新的火箭芯片版本可以在主流火箭芯片。 在ZCU102上，使用Vivado v2017.1进行单核配置的时钟频率（时钟速度）可以达到195 MHz。 请参阅以了解如何使用此存储库。 注意：我最近在删除了sed命令，因为它在主机OS环境中不可靠。 而是，在第一次构建之前，只需在245行中插入新行|aarch \ 。 关于SD卡（将硬件和软件堆栈带入FPGA），请参见 。 当前流已在以下主机环境中经过测试： 软件 版本 作业系统 16.04.1-Ubuntu与4.15.0-64-generic内核 重击 4.3.48

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.

包括以下内容: UX3328S规格书_V1.2.pdf UX3328应用笔记v2.0.pdf UX3328S GUI用户手册 V0.5.pdf UX3328S GUI - Ver1.0.1.6.rar

Springer - Programming Many-Core Chips.2011

Yidu-N4K 数据集源自CHIP 2019 评测任务一，即“临床术语标准化任务”的数据集。 临床术语标准化任务是医学统计中不可或缺的一项任务。临床上，关于同一种诊断、手术、药品、检查、化验、症状等往往会有成百上千种不同的写法。

Google TPU V1/2/3芯片对比，以及V3性能分析